1. Field
The present invention relates generally to phase locked loops, and more specifically to hybrid analog-digital phase locked loops.
2. Background
Phase-locked loops (PLLs) generate signals relative to a reference signal. The phase-locked loop circuit adjusts a frequency of a PLL output signal based on differences in phase and/or frequency of the reference signal and the output signal. The frequency of the output signal is increased or decreased based on the difference. The phase-locked loop is, therefore, a control system using negative feedback. Phase-locked loops are used in electronics such as radios, telecommunication circuits, and computers as well as other devices.
PLLs often use a resonant-tuned voltage controlled oscillator (VCO) to generate the PLL output signal. A resonant tuned VCO often includes a capacitive device and a resonant inductor-capacitor (LC) circuit. The capacitive device typically includes at least one varactor having a capacitance that responds to a tuning voltage to change the frequency of the PLL output signal.
Some conventional PLL include one more digital components. Such PLLs have advantages over analog loops in some respects. Unfortunately, these PLLs also have some disadvantages. Accordingly, there is need for a PLL that has advantages of both analog and digital loops